The present invention relates to a semiconductor integrated circuit, and more particularly to an input buffer circuit for converting a TTL(TTL:Transistor transistor logic) level signal supplied from an outside into an internal CMOS level signal.
As a semiconductor integrated circuit, a semiconductor memory device is activated from signals such as an address, a control signal or data supplied from a system and then performs corresponding operation like read or write operation. The levels of the signals input from the system are generally converted into the TTL level. In order for CMOS circuit of the internal of a chip to perform the corresponding operate, there should be a circuit to convert the TTL level into the CMOS level like the input buffer. Meanwhile, such an input buffer is connected to a PIN or a PAD on the same chip and then shapes the address, the control signal or the data input through the PIN or the PAD.
In typical, since the semiconductor memory device uses an operating voltage of 5 volts or 3.3 volts, the input buffer exclusively used in the 5 volts or the input buffer exclusively used in 3.3 volts is actually restricted by a kind of system. Therefore, the input buffer should be designed to adapted to all the systems employing the 5 volts or 3.3 volts. Further, even if the operating voltage is varied, the input buffer should maintain its original characteristic of shaping input signals, and also should be stably driven.
FIG. 1 shows an input buffer circuit capable of corresponding to the variation of an operating voltage. In the construction, the input buffer circuit shown in FIG. 1 further comprises, in addition to a PMOS transistor 4 having one inverter which inputs an external signal Vin and an NMOS transistor 8, a PMOS transistor 10 having the other inverter stable to the operating voltage of 3.3 volts and an NMOS transistor 12. Therefore, the input buffer circuit of FIG. 1 is to implement a double use of the operating voltages of 5 volts and 3.3 volts. Meanwhile, in FIG. 1, a mask indicated by a dotted line block is used as one option and whose change is determined according to the operating voltage. For example, in case that a power voltage Vcc becomes 5 volts, the voltage level of the power voltage Vcc charged to an outputting node 6 is enough high. Thereby, the input buffer can be operated by only the PMOS transistor 4 and the NMOS transistor 8. However, in case that the power voltage Vcc becomes 3.3 volts, the PMOS transistor 4 requires much time to charge the voltage level of the power voltage Vcc charged to the outputting node 6. Thereby, input "high" characteristic VIH becomes bad and it is difficult to perform an access operation at high speed. Accordingly, the PMOS transistor 10 and the NMOS transistor 12 should be further included. Consequently, when the input buffer shown in FIG. 1 is employed in the system of 3.3 volts, the mask maintaining the dotted line block should be used, whereas when the input buffer is employed in the system of 5 volts, the other mask disconnecting the dotted line block should be used. Therefore, a company producing the chip must change the design thereof according to the operating voltage of the system. Further, the company has a large load of adding the mask. As known to one skilled in the art, it is clear that an additional use of the mask has a serious influence on production cost and production time. Meanwhile, in FIG. 1, there aries an inconvenience in that the mask should be used as two stages in order to apply the circuit to all the systems of 5 volts and 3.3 volts.